Scheduling Divisible Loads with Processor Release Times and Finite Size Buffer Capacity Constraints in Bus Networks

摘要

In this paper we address the problem of processing a computationally intensive divisible load with high memory requirements on a bus network. Each network node is assumed to have a limited memory capacity (buffer space), while at the same time being available for processing after a specific time (release time). The combined influence of the release times, as well as the limited buffer capacity available, is considered in the problem formulation, with the objective to minimize the overall processing time of the divisible load. In the existing literature, these two issues have been considered independently, although in practice, they are commonly found to coexist. The Multi-Installment Balancing Strategy (MIBS) presented in this paper, manages to address both of these constraints by building on-top of the analytical solutions derived by a buffer capacity-unaware approach. MIBS monitors the available resources and adapts the processing and communication phases according to their availability. Towards this goal both single and/or multi-installment scheduling is utilized. The description of the algorithms accompany simulation experiments that highlight the behavior of MIBS. It should be stressed that the use of MIBS allows the processing of loads that exceed by far the total memory capacity of the available machines, while at the same time exhibiting processing times that match the ones predicted by strategies that ignore the memory constraints.