A hardware implementation of 128-bit block cipher - camellia

摘要

In this paper, we report our hardware implementation of a 128-bit block cipher, Camellia, concentrating on a small implementation As a result, our design achieves very small size, for example 6,374 gates on 0.18μmCMOS ASIC and 1,396 slices on Virtex1000E series, which work in 40 cycles/block.