Preemptive Hardware Multitasking on Dynamically Partially Reconfigurable FPGAs - Hardware and Reconfiguration Layers

摘要

Preemption techniques for HW (hardware) tasks have been studied in order to improve their responsiveness and to allow implementation of a blocking call within a task. In order to support preemption of HW tasks at a level of a conventional software multitasking OS, context saving and restoring mechanisms must be implemented in hardware and appropriate software programming interface, abstracting their implementation details, provided. This paper presents a solution for efficient preemptive hardware multitasking on Xilinx Virtex FPGAs. It comprises an embedded system framework and design flow back-end tools which automate generation of preemptable HW tasks and configuration files used by the framework. The framework features in a high-speed reconfiguration/readback controller and a low-footprint configuration layer. The layer provides an easy-to-use API (Application Programming Interface) facilitating management of the preemption process, which could be used as a base of a fully fledged preemptive SW/HW multitasking OS. The framework has been implemented on top of the Virtex-4 FPGAs and showed promising results.