A hardware/software cosynthesis system for processors based on reducing operation word length with memory interface specification

摘要

Let us consider to reduce an area of a processor by shortening the operation word length from n to n/2. In this ease, we generally need to excute an operation instruction at least two times in order to obtain n-bit result. However, assume that internal variables in an application program uses only n/2 bits. In this case, we need to execute the operation instruction only once. We have proposed a hardware/software cosynthesis system for processors. In the system, we assume that data length of applications program equals to operation word length of a processor core. This paper proposes an algorithm for shortening an operation word length. The algorithm repeatedly replaces each n hit operation instruction with one or more n/2 bit operation instructions depending on internal variable precision.