Speculative memory access mechanism for thread-level speculation

摘要

To support efficiently speculative memory access for thread-level speculation, we have proposed a cache mechanism without burst writeback when a speculation succeeds. The proposed mechanism maintains distributedly the ordering of speculative versions by using the binary relation, and resolves data dependencies by speculative forward. We have written a simulator for run-time loop restructuring method, and evaluated the performance. The loop construct of "swim" is executed three times faster by using four processors than sequential execution.