A Method of Clock Synchronization for Power Packet Dispatching Parameters Optimization in Clock Synchronization

摘要

This paper proposes a method of clock synchronization for power packet dispatching. In a power packet dispatching system, power packets are generated in a mixer and transmitted to a router, so that the clock synchronization between the mixer and the router is required to recognize the packet signal and receive the electric power correctly. According to the simulation result in Simulink of MATLAB, it is confirmed that the clock synchronization can be achieved by using charge-pump phase-locked loops (CPPLL) and can be detected by a synchronization detect circuit. The settling time is defined as the time duration from the beginning of a packet to the time when the synchronization is achieved. The quiescent frequency, input sensitivity of Voltage-Controlled Oscillator (VCO), and parameters of low pass filter in CPPLL are discussed to minimize the settling time in clock synchronization.