An Exploratory Design Study of a 16 x 16 Static Random Access Memory Using Silicon Nanowire Transistors

摘要

This study presents a nanometer-scale 16 × 16 Static Random Access Memory (SRAM) design using vertical, undoped, dual metal work function silicon nanowire transistors. The design cycle starts with determining individual metal gate work function of each N and P-channel Metal Oxide Semiconductor transistor to produce a 300 mV threshold voltage. Wire radius and effective channel length are both varied to find a common body geometry that minimizes static and dynamic power dissipations while maximizing ON current for both N and P-channel transistors. Once the optimal device dimensions are defined, a 16 × 16 SRAM is bui its transient performance, power dissipation and layout area are measured. Post-layout simulation results indicate that the worst-case read and write access times of the SRAM are 133 ps and 98 ps, respectively; its power dissipation is 331 μW during a read and 251 μW during a write operation at 500 MHz. The SRAM layout occupies approximately 16 μm{sup}2.