PEALL4: a 4-channel, 12-bit, 40-MSPS, Power Efficient and Low Latency SAR ADC

摘要

The PEALL4 chip is a Power Efficient And Low Latency 4-channels, 12-bit and 40-MSPS successive approximation register (SAR) ADC. It was designed featuring a very short latency time in the context of ATLAS Liquid Argon Calorimeter phase I upgrade. Moreover this design could be a good option for ATLAS phase II and other High Energy Physics (HEP) projects. The full functionality of the converter is achieved by an embedded high-speed clock frequency conversion generated by the ADC itself. The design and testing results of the PEALL4 chip implemented in a commercial 130nm CMOS process are presented. The size of this 4-channel ADC with embedded voltage references and sLVS output serializer is 2.8x3.4 mm~2. The chip presents a short latency time less than 25 ns defined from the very beginning of the sampling to the last conversion bit made available. A total power consumption below 27mW per channel is measured including the reference buffer and the sLVS serializer.