Synthesis and Analysis of Timing Constraints for Real-Time Embedded Systems using Modular TER nets

摘要

In developing time-critical systems such as real-time systems and embedded systems, it is important to check timing conflicts between timing requirements as earlier as possible. For checking timing conflicts, at least, a formal notation should be introduced for a concrete and unambiguous requirements specification. However, in an earlier development phase it is not easy to describe timing requirements by using formal methods. In this paper, we propose a systematic procedure for transforming and synthesizing timing scenarios of real-time and embedded systems by Modular TER nets. And an analysis procedure for checking timing conflicts is provided. Using the generated formal model, users can check the timing inconsistencies among requirements before designing and implementing real-time embedded systems.