Ultra Low leakage Datapath Design

摘要

Technology scaling to deep submicron technology has facilitated the integration of multi-million gate systems on a single chip. Speed and performance of these systems are ever increasing. What we are paying for this gain is in terms of power, cost and complexity of the design. Increase in dynamic power as well standby power has created a bottleneck for the ultra large integrations. Device scaling and hence the threshold voltage scaling has increased leakage power many folds [1]. Many methods in design as well as process are being used to tackle the issue. Power gating is one of those [3]. Here we are going to use a variation of power gating where supply is split for both VDD and VSS. This split supply is provided to a series of interface devices making leakage responsible devices in reverse bias or complete cut-off from supply & thus a manifold reduction in leakage power compared to other methodologies.