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Companies Join Forces in Systems Development

机译:公司联手进行系统开发

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SEMATECH researchers have identified a dual damascene method for interconnect integration that could achieve an aggressive industry target for ultra low-k dielectric materials in semiconductor manufacturing. The two-level metal, dual damascene process uses two Zirkon interlayer dielectric (ILD) films from Rohm and Haas Electronic Materials to demonstrate a copper/ultra low-k (ULK) integration with a k-effective (k_(eff)) value of 2.5. 2.5 is the target set out by the International Technology Roadmap for Semiconductors (ITRS) for the 45 nm technology generation. By using ULK dielectric films and newly developed flows, the process achieves a lower k-effective result. Selected details of the process were to be presented Sept. 27 in a paper-submitted to the Advanced Metalization Conference (AMC) at Colorado Springs, CO. "The dual damascene integration that our team developed offers a potential solution for blocking precursor penetration and minimizing process-induced damage typically observed with ULK dielectrics containing interconnected pores," said Ward Engbrecht, lead author and a SEMATECH copper low-k integration project engineer. Ultra low-k films are porous materials that are much less dense than organosilicate glasses, the starting material for advanced interconnect technology dielectrics. ULK is critical to advanced semiconductor manufacturing because it will allow metal lines to be packed closer together on a chip with less capacitance-driven delay, which slows chip performance.
机译:SEMATECH研究人员已经确定了用于互连集成的双镶嵌方法,该方法可以实现针对半导体制造中超低k介电材料的激进行业目标。双层金属双镶嵌工艺使用了Rohm and Haas Electronic Materials的两个Zirkon层间电介质(ILD)膜,以证明铜/超低k(ULK)集成度的k-有效(k_(eff))值为2.5。 2.5是国际半导体技术路线图(ITRS)为45纳米技术一代设定的目标。通过使用ULK介电膜和新开发的流程,该工艺可获得较低的k效果结果。该工艺的选定细节将在9月27日提交给科罗拉多州科罗拉多斯普林斯举行的高级金属化会议(AMC)的论文中提出。“我们团队开发的双镶嵌集成提供了一种潜在的解决方案,可阻止前驱物的渗透并最大程度地减少此类污染。过程引起的损坏,通常是在包含互连孔的ULK电介质中观察到的,”主要作者和SEMATECH铜低k集成项目工程师Ward Engbrecht说道。超低k膜是多孔材料,其密度远低于有机硅酸盐玻璃,后者是先进互连技术电介质的起始材料。 ULK对于先进的半导体制造至关重要,因为ULK可以使金属线在芯片上紧密排列在一起,而电容驱动的延迟较小,这会降低芯片性能。

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