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首页> 外文期刊>Surface & Coatings Technology >Influence of substrate bias voltage on deposition behavior and microindentation hardness of Ti-Si-N coatings by a hybrid coating system of arc ion plating and sputtering techniques
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Influence of substrate bias voltage on deposition behavior and microindentation hardness of Ti-Si-N coatings by a hybrid coating system of arc ion plating and sputtering techniques

机译:电弧离子镀和溅射技术混合涂层系统中衬底偏压对Ti-Si-N涂层沉积行为和显微压痕硬度的影响

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In this work, the influence of substrate bias voltage on deposition behaviors such as deposition rate, film composition, macroparticles and surface roughness were investigated for the Ti-Si-N coatings deposited on WC-Co substrates by a hybrid coating system of arc ion plating and sputtering techniques. Also, the hardness and Young's modulus of Ti-Si-N coatings by nanoindentation tests were investigated with the substrate bias voltage. Applying substrate bias voltage up to -100 V during Ti-Si-N deposition resulted in the significant diminution of macroparticles and smoothening of surface morphology. The micro-indentation hardness and Young's modulus values were also significantly increased at a bias voltage of -100 V, and showed the highest values of similar to60 and similar to700 GPa, respectively. However, increasing the negative bias voltage above -100 V caused the continual reduction of those properties, and reduced both deposition rate and Si content in the Ti-Si-N coatings. (C) 2003 Elsevier B.V. All rights reserved. [References: 21]
机译:在这项工作中,研究了通过电弧离子镀混合涂层系统在WC-Co基底上沉积的Ti-Si-N涂层对基底偏压对沉积行为的影响,例如沉积速率,膜组成,大颗粒和表面粗糙度。和溅射技术。此外,还通过纳米压痕测试研究了Ti-Si-N涂层的硬度和杨氏模量,并采用了衬底偏置电压。在Ti-Si-N沉积过程中施加高达-100 V的衬底偏置电压会导致大颗粒的显着减小和表面形态的平滑化。在-100 V的偏置电压下,微压痕硬度和杨氏模量值也显着增加,并且分别显示出最高的相似值60和相似的700 GPa。但是,将负偏置电压提高到-100 V以上会导致这些性能的持续降低,并降低Ti-Si-N涂层中的沉积速率和Si含量。 (C)2003 Elsevier B.V.保留所有权利。 [参考:21]

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