Model checking memoryful linear-time logics over one-counter automata

摘要

We study complexity of the model-checking problems for LTL with registers (also known as freeze LTL and written LTL↓) and for first-order logic with data equality tests (written FO(～, <, +1)) over one-counter automata. We consider several classes of one-counter automata (mainly deterministic vs. nondeterministic) and several logical fragments (restriction on the number of registers or variables and on the use of propositional variables for control states). The logics have the ability to store a counter value and to test it later against the current counter value. We show that model checking LTL↓ and FO(～, <, +1) over deterministic one-counter automata is PSPACE-complete with infinite and finite accepting runs. By contrast, we prove that model checking LTL↓ in which the until operator U is restricted to the eventually F over nondeterministic one-counter automata is Σ_1~1-complete [resp. Σ_1~0-complete] in the infinitary [resp. finitary] case even if only one register is used and with no propositional variable. As a corollary of our proof, this also holds for FO(～, <, +1) restricted to two variables (written FO_2(～, <, +1)). This makes a difference with respect to the facts that several verification problems for one-counter automata are known to be decidable with relatively low complexity, and that finitary satisfiability problems for LTL↓ and FO_2(～, <, +1) are decidable. Our results pave the way for model checking memoryful (linear-time) logics over other classes of operational models, such as reversal-bounded counter machines.