Optimization of Leakage Current and Leakage Power of Full Adder by Using Self-Controlled Voltage Level Technique in Nanometer Regime

摘要

Full adder is an essential component for the design and development of all types of processors viz. digital signal processors (DSP), microprocessors etc. Adders are the core element of complex arithmetic operations like addition, multiplication and division etc. optimization of power is very important issue in low voltage and low power applications. In this work the impact of leakage on Full Adder is described and two approaches are used for reducing leakage current in detail. In one approach the supply voltage is reduced while in other the potential of the ground node is increased. In both the approaches the effective voltage across Full Adder cell is reduced in standby mode using a dynamic self controllable switch (SVL Switch). Simulation result is performed at different voltage levels e.g., 1 V, 0.9 V and 0.7 V using cadence virtuoso tool based on for 45 nm CMOS technology show that the scheme in which supply voltage level is reduced is more efficient in reducing leakage than the one in which ground node potential is raised.