Analysis of Passive Charge Sharing-Based Segmented SAR ADCs

摘要

This article presents the theoretical analysis of passive charge sharing-based segmented successive-approximation-register (SAR) analog-to-digital converter (ADC), where the precise reference source in a capacitive digital-to-analog converter (CDAC) is replaced by a capacitor that is eta times larger than its bit capacitor and precharged to the reference level, known as a reference charge reservoir (RCR). A segmented SAR-ADC uses a coarse SAR-ADC to compute some most significant bits (MSBs). Four methods, namely aligned switching (AS) with bitwise RCRs, AS with a subsample-wise RCR, detect-and-skip aligned switching (DAS-AS) with bitwise RCRs, and DAS-AS with a subsample-wise RCR are introduced for setting fine MSBs. Closed-form analytic expressions of the reference error due to the finite reference capacitance are derived and validated by behavioral modeling and circuit simulation of an 11-bit 50 MS/s segmented SAR ADC in 65-nm CMOS technology. The error expressions can be used to select one of the four methods for setting the fine MSBs and to determine eta for the required linearity or for implementing digital circuitry for precise error correction.