System design for pixel-parallel image processing

摘要

A system design for performing low-level image processing tasks innreal time is presented. The design is based on large processor-per-pixelnarrays implemented using integrated circuit technology. Two integratedncircuit architectures are summarized: an associative parallel processornand a parallel processor employing DRAM cells. In both architectures,nthe layout pitch of one-bit-wide logic is matched to the pitch of memoryncells to form high-density processing element arrays. The system designnfeatures an efficient control path implementation, providing highnprocessing element array utilization without demanding complexncontroller hardware. Sequences of array instructions are generated by anhost computer before processing begins, then stored in a simplencontroller. Once processing begins, the host computer initiates storednsequences to perform pixel-parallel operations. A programming frameworknimplemented using the C++ programming language supports applicationndevelopment. A prototype system employs associative parallel processorndevices, a controller, and the programming framework. Three samplenapplications, smoothing and segmentation, median filtering, and opticalnflow, establish the suitability of the system for real-time imagenprocessing