Placement-Based Nonlinearity Reduction Technique for Differential Current-Steering DAC

摘要

This paper presents a switching scheme-based placement method to reduce the effect of various sources of nonlinearity arising due to layout routing parasitic in a current-steering digital-to-analog converter (DAC), thereby providing excellent static and dynamic performance. The proposed technique reduces both the individual and the cumulative effect of different nonidealities. Improvement in both the static and the dynamic performance is observed when compared with that provided by conventional common centroid placement. A 10-bit 500-MHz differential current-steering DAC has been designed and evaluated in 65-nm CMOS process as a case study, which provides a -dB spurious-free dynamic range at a 122-Ms/s input frequency.