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机译:非准循环LDPC码的设计和高效的硬件实现方案
Department of Electronic Engineering, Tsinghua University, Beijing, China;
Department of Electronic Engineering, Tsinghua University, Beijing, China;
School of Aerospace, Tsinghua University, Beijing, and with the EDA Laboratory, Research Institute of Tsinghua University in Shenzhen, Shenzhen, China;
Department of Electronic Engineering, Tsinghua University, Beijing, China;
Decoding; Parity check codes; Hardware; Algorithm design and analysis; Random access memory; Message passing; Standards;
机译:非准循环LDPC码的设计和高效的硬件实现方案
机译:灵活的LDPC解码器实现的硬件有效节点处理单元架构
机译:针对无线传感器网络的高度安全,硬件高效的QCLDPCrncode非线性加密系统的FPGA实现
机译:基于最小和算法的高效高级方法论,用于LDPC解码器的设计,仿真和硬件实现
机译:无线衰落通道使用LDPC代码的无线误差保护方案的设计与实现HEVC比特流
机译:分层最小和迭代构建的一个区域高效和高吞吐量的后验概率LDPC解码器
机译:基于Protograph LDPC的联合信源和信道编码的硬件实现和解码设计