Modelling Radiation-Induced Failures in FPGAs Using the Dynamic Flowgraph Methodology

摘要

DFM was used to model an FPGA-based Vanadium signal compensator and trip logic test system. Various SEEs and probabilities from the literature were added to the model to allow for a detailed analysis on the effects of those SEEs on the FPGA-based system. It was observed that SEEs can have a serious effect on the system, such as causing failures in the FPGA hardware and/or logic, and can lead to "Fail to Trip" or "Spurious Trip" events. From this preliminary work, DFM has the potential to be able to model the effects of these SEE failures on an FPGA-based system. Future work on this subject includes an expanded number of failure modes (such as ageing failures and logic failures), discussing defenses against SEE (such as redundancy and error detection/correction codes), and the comparison of DFM with other established hazard analysis methods, in order to create a more realistic model.