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Spacer engineered Trigate SOI TFET: An investigation towards harsh temperature environment applications

机译:垫片设计的Trigate SOI TFET:针对恶劣温度环境应用的调查

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In this paper, a novel N-channel Tunnel Field Effect Transistor (TFET) i.e., Trigate Silicon-ON-Insulator (SOI) N-TFET with high-k spacer is proposed for better Sub-threshold swing (SS) and OFF-state current (I_(OFF)) by keeping in mind the sensitivity towards temperature. The proposed model can achieve a Sub-threshold swing less than 35 mV/decade at various temperatures, which is desirable for designing low power CTFET for digital circuit applications. In N-TFET source doping has a significant effect on the ON-state current (I_(ON)) level; therefore more electrons will tunnel from source to channel region. High-k Spacer i.e., HfO_2 is used to enhance the device performance and also it avoids overlapping of transistors in an integrated circuits (IC's). We have designed a reliable device by performing the temperature analysis on Transfer characteristics. Drain characteristics and also on various performance metrics like ON-state current (I_(ON)). OFF-state current (I_(OFF)). I_(ON)/ I_(OFF). Trans-conductance (g_m), Trans-conductance Generation Factor (TGF), Sub-threshold Swing (SS) to observe the applications towards harsh temperature environment.
机译:本文提出了一种新型的具有高k隔离层的N沟道隧道场效应晶体管(TFET),即Trigate导通硅绝缘体(SOI)N-TFET,以改善亚阈值摆幅(SS)和截止状态牢记对温度的敏感度,从而获得最大电流(I_(OFF))。所提出的模型可以在各种温度下实现低于35 mV /十倍的亚阈值摆幅,这对于设计用于数字电路应用的低功率CTFET是理想的。在N-TFET中,源极掺杂对导通状态电流(I_(ON))的水平有重要影响。因此,更多的电子将从源极隧穿到沟道区。高k间隔物(即HfO_2)用于增强设备性能,并且还可避免集成电路(IC)中晶体管的重叠。通过对转印特性进行温度分析,我们设计了一种可靠的设备。漏极特性以及各种性能指标,例如导通状态电流(I_(ON))。断态电流(I_(OFF))。 I_(ON)/ I_(OFF)。跨导(g_m),跨导生成因子(TGF),亚阈值摆幅(SS),以观察在恶劣温度环境下的应用。

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