A 14-port 3.8-ns 116-word 64-b read-renaming register file

摘要

A 116-word by 64-b register file for a 154 MHz four-issue superscalar processor renames read addresses and reads data in a single operation. A 10-port, 116-word tag comparison unit and a rename logic unit use static-bit-line techniques in the comparison logic. Pulsed-power sense amplifiers achieve a 3.8-ns read delay while dissipating 31% less power than a nonpulsed circuit.