A 240-Mbps, 1-W CMOS EPRML read-channel LSI chip using aninterleaved subranging pipeline A/D converter

摘要

A 3.3-V, 1-W, 240-Mbps extended-partial-responsenmaximum-likelihood read/write-channel large-scale-integration chip fornhard disk drives has been developed. Power consumption of 1 W wasnachieved by using a 3.3-V power supply, a 0.4-Μm CMOS process, and an3.3-V CMOS analog circuit design. Our approach to achieving a highntransfer rate of 240 Mbps was to develop an interleaved subrangingnpipeline lookahead analog/digital (A/D) converter architecture. Thenpower consumption of this A/D converter is 200 mW at 255 MHz. Thenread-mode channel path combines an acquisition-mode analog phase-lockednloop (PLL) and a tracking-mode precision digital PLL, enabling the usenof a long-latency pipeline A/D converter in the digital PLL.nConsequently, a bit error rate of 10**(-9) at a signal-to-noise ratio ofn24.5 dB has been achieved