A 3.3-V, 4-Mb nonvolatile ferroelectric RAM with selectively drivendouble-pulsed plate read/write-back scheme

摘要

This paper presents, for the first time, a 4-Mb ferroelectricnrandom access memory, which has been designed and fabricated withn0.6-Μm ferroelectric storage cell integrated CMOS technology. Innorder to achieve a stable cell operation, novel design techniques robustnto unstable cell capacitors are proposed: (1) double-pulsed platenread/write-back scheme; (2) complementary data preset referencencircuitry; (3) relaxation/fatigue/imprint-free reference voltagengenerator; (4) open bitline cell array; (5) unintentional power-off datanprotection scheme. Additionally, to improve cell array layout efficiencyna selectively driven cell plate scheme has been devised. The prototypenchip incorporating these circuit schemes shows 75 ns access time andn21-mA active current at 3.3 V, 25°C, 110-ns minimum cycle. The diensize is 116 mm2 using 9 Μm2,none-transistor/one-capacitor-based memory cell, twin-well, single-poly,nsingle-tungsten, and double-Al process technology