A 250-Mb/s/pin, 1-Gb double-data-rate SDRAM with a bidirectionaldelay and an interbank shared redundancy scheme

摘要

This paper describes three circuit technologies indispensable fornhigh-bandwidth multibank DRAM's. (1) A clock generator based on anbidirectional delay (BDD) eliminates the output skew. The BDD measuresnthe cycle time as the quantity charged or discharged of an analognquantity, and replicates it in the next cycle. This achieves a 0.18-mmn2, two-cycle-lock clock generator operating from 25 to 167nMHz with a 30-ps resolution. (2) A quad-coupled receiver eliminates theninternal skew caused by the difference between a rise input and a fallninput by 40%. (3) An interbank shared redundancy scheme (ISR) with anvariable unit redundancy (VUR) efficiently increases yield in multibanknDRAM's. The ISR allows redundancy match circuits to be shared with twonor more banks. The VUR allows the number of units replaced to benvariable. These circuit technologies achieved a 250-Mb/s/pin, 8-bank,n1-Gb double-data-rate synchronous DRAM