A digitally controlled phase-locked loop with a digitalphase-frequency detector for fast acquisition

摘要

A digitally controlled phase-locked loop (DCPLL) that achievesnfast acquisition by employing a digital phase-frequency detector (DPFD)nand a variable loop gain scheme was developed for an advanced clocknsynthesizer and was fabricated in a 3.3-V 0.6-Μm CMOS process. ThenDPFD was developed to measure the frequency difference and to generatendigital outputs corresponding to the difference. Using these features,nthe DCPLL achieves ideally one-cycle frequency acquisition whennprogrammed with an appropriate gain. The experimental results show thatnthe fabricated DCPLL exhibits three-cycle and one-cycle frequencynacquisitions, when locking to 400 MHz (VCO at 800 MHz) and 200 MHz (VCOnat 400 MHz), respectively