A 1.8-V embedded 18-Mb DRAM macro with a 9-ns RAS access time andmemory-cell area efficiency of 33%

摘要

A 1.8-V embedded 18-Mb DRAM macro with a 9-ns row-address-strobenaccess time and memory-cell area efficiency of 33% has been successfullyndeveloped with a single-side interface architecture, high-speed circuitndesign, and low-voltage design. In the high-speed circuit design, anmultiword redundancy scheme and Y-select merged sense scheme arendeveloped to achieve the performance goal. In the low-voltage design, andual-complement charge-pump scheme and a decoupling capacitor utilizingna tantalum-oxide capacitor are developed to retain high performance atnlow supply voltage