High-Bit-Rate Low-Power Decision Circuit Using InP-InGaAs HBT Technology

摘要

We have successfully designed and fabricated a high-bit-rate low-power decision circuit using InP-InGaAs heterojunc-tion bipolar transistors (HBTs). Its main design feature is the use of a novel master-slave D-type flip-flop (MS-DFF) as the decision circuit core to boost the operating speed. We achieved error-free operation at a data rate of up to 60 Gb/s using an undoped-emitter InP-InGaAs HBT with a cutoff frequency f{sub}T of approximately 150 GHz and a maximum oscillation frequency f{sub}(max) of approximately 200 GHz. Our decision circuit operates approximately 15%. faster than one with a conventional MS-DFF core. We also achieved 90-Gb/s operation with low power consumption of 0.5 W using an InP-InGaAs DHBT exhibiting f{sub}T and f{sub}(max) of 232 and 360 GHz, respectively. These results demonstrate that InP-based HBTs and our novel MS-DFF are attractive for making ultrahigh-perfor-mance ICs for future optical communications systems operating at bit rates of 100 Gb/s or more.