An Inductive-Coupling DC Voltage Transceiver for Highly Parallel Wafer-Level Testing

摘要

A small-size inductive-coupling dc voltage transceiver for highly-parallel wafer-level testing is experimentally demonstrated in 90-nm CMOS technology, which can reduce the total cost of a low-price IC by 18%. In order to carry out dc tests, the proposed transceiver outputs dc voltage to the die-under-test (DUT) without any area-consuming digital circuits. In addition, digital calibration with digital feedback channel which calibrates the output dc voltage enables the removal of calibration circuits on the DUT. All of the circuits for dc tests are implemented into the area of an inductor (100 $mu{hbox {m}} times ,$100 $mu{hbox {m}}$). The proposed dc voltage transmission is successfully demonstrated with 6-bit resolution.