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A 1.27 GHz, All-Digital Spread Spectrum Clock Generator/Synthesizer in 65 nm CMOS

机译:采用65 nm CMOS的1.27 GHz全数字扩频时钟发生器/合成器

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摘要

Spread spectrum clocking is an effective solution to reduce the electromagnetic interference produced by digital chips, using a clock signal with a frequency that is intentionally swept (frequency modulated) within a certain frequency range, with a predefined modulation profile. We present the implementation of an all-digital spread spectrum clock generator. The circuit is realized by using a design flow completely based on standard cells and is able to perform clock spreading with an arbitrary modulation profile and a modulation frequency up to 5 MHz. The circuit uses two digitally controlled delay lines driven by a digital modulator to synthesize the output waveform. A replica delay line is employed in a real-time measurement circuit to track process, voltage and temperature variations. A chip has been implemented in a 65 nm CMOS technology. The chip is able to generate signals up to 1.27 GHz. The measured peak level reduction of the clock spectrum, at 750 MHz output frequency, is 20.5 dB with a 6% modulation depth. The power dissipation is 44 mW @ 1.27 GHz.
机译:扩频时钟控制是一种有效的解决方案,它使用具有一定频率范围内有意扫描(频率调制)的频率的时钟信号和预定义的调制配置文件来减少数字芯片产生的电磁干扰。我们介绍了一个全数字扩频时钟发生器的实现。该电路是通过使用完全基于标准单元的设计流程实现的,并且能够以任意调制配置文件和高达5 MHz的调制频率执行时钟扩展。该电路使用两条由数字调制器驱动的数控延迟线来合成输出波形。实时测量电路中使用复制延迟线来跟踪过程,电压和温度变化。芯片已采用65 nm CMOS技术实现。该芯片能够产生高达1.27 GHz的信号。在750 MHz输出频率下,测得的时钟频谱峰值电平降低为20.5 dB,调制深度为6%。在1.27 GHz时,功耗为44 mW。

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