A Low-Voltage Bulk-Drain-Driven Read Scheme for Sub-0.5 V 4 Mb 65 nm Logic-Process Compatible Embedded Resistive RAM (ReRAM) Macro

摘要

ReRAM is a promising candidate for on-chip low-VDD NVM due to its superior write behavior, particularly for frequent-read-seldom-write applications. Nonetheless, this approach requires a robust and fast low-VDD read scheme. Current-mode sense amplifiers (CSA) are commonly used in NVM; however, they suffer low-yield and degraded speed at a low VDD, due to an insufficient on-off current difference ($I _{ON-OFF}$) and the need for large voltage head room (VHR). This study developed a body-drain-driven (BDD) read scheme to suppress VHR and provide resistance-aware dynamic bitline bias voltage for increasing $I _{ON-OFF}$ . The proposed scheme achieved 2.1 $,times$ faster read speed, $> 1.7times$ higher yield, and $> 2times$ longer BL length at 0.5 V VDD than conventional CSAs. A fabricated 65 nm 4 Mb ReRAM macro using the proposed read scheme and our logic-compatible ReRAM cell achieved a 45 ns random read access time at ${rm VDD}=0.5~{rm V}$. The proposed sensing scheme also achieved a 0.32 V VDDmin.