首页> 外文期刊>IEEE Journal of Solid-State Circuits >40-nm Embedded Split-Gate MONOS (SG-MONOS) Flash Macros for Automotive With 160-MHz Random Access for Code and Endurance Over 10 M Cycles for Data at the Junction Temperature of 170 $^{circ}$C
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40-nm Embedded Split-Gate MONOS (SG-MONOS) Flash Macros for Automotive With 160-MHz Random Access for Code and Endurance Over 10 M Cycles for Data at the Junction Temperature of 170 $^{circ}$C

机译:适用于汽车的40 nm嵌入式分栅MONOS(SG-MONOS)闪存宏,在170°C的结温下具有160 MHz随机访问的代码和超过10 M周期的耐久性,可存储数据

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First-ever 40-nm embedded split-gate MONOS (SG-MONOS) flash macros for automotive micro-controller unit (MCU) have been successfully developed. A SG-MONOS cell realizes high performance with low power consumption and intrinsically high data reliability thanks to the combination of split-gate and charge-trapping structure. In addition, newly developed circuit techniques greatly enhance the advantages of SG-MONOS cells and enable fast and reliable operations even at the junction temperature (Tj) of 170 $^{circ}$C with small peripheral circuit area; 1) a sense amplifier with digital offset cancellation (SA-DOC) provides fast read operation over 160 MHz; 2) adaptable program current control scheme (APCCS) and intelligent erase scheme (IES) significantly decrease the program and erase time, which also results in improving the memory cells' reliability; and, 3) 3-D stacked unit capacitors achieve area-efficient charge pump. Two types of embedded flash (eFlash) macros with these technologies, code macro of 2 MB and data macro of 64 KB, were fabricated in a 40-nm eFlash process. The code macro demonstrates the capability of 160-MHz random read operation at ${rm Tj}=hbox{ 170 }^{circ}$C, reaching 5.1 GB/s read throughput by simultaneous 256 bits read-out from two code macros. The data macro achieves the program/erase endurance over 10 million cycles at ${rm Tj}=hbox{ 170 }^{circ}$C without any software-assisted techniques.
机译:成功开发了用于汽车微控制器单元(MCU)的首款40纳米嵌入式分裂门MONOS(SG-MONOS)闪存宏。 SG-MONOS单元通过分离栅和电荷陷阱结构的结合,实现了高性能,低功耗和本质上较高的数据可靠性。此外,新开发的电路技术极大地增强了SG-MONOS电池的优势,即使在结温(Tj)为170 $ C且外围电路面积较小的情况下,也能实现快速可靠的操作; 1)具有数字失调消除功能的感测放大器(SA-DOC)提供160 MHz以上的快速读取操作; 2)适应性编程电流控制方案(APCCS)和智能擦除方案(IES)大大减少了编程和擦除时间,这也提高了存储单元的可靠性。 3)3D堆叠单元电容器实现了面积有效的电荷泵。采用这些技术的两种类型的嵌入式闪存(eFlash)宏,即2 MB的代码宏和64 KB的数据宏,是在40 nm eFlash工艺中制造的。代码宏演示了在$ {rm Tj} = hbox {170} ^ {circ} $ C的情况下160 MHz随机读取操作的能力,通过同时从两个代码宏中读取256位,达到了5.1 GB / s的读取吞吐量。数据宏无需任何软件辅助技术即可在$ {rm Tj} = hbox {170} ^ {circ} $ C的情况下实现超过1000万个循环的编程/擦除持久性。

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