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首页> 外文期刊>Solid-State Circuits, IEEE Journal of >A 27 mW Reconfigurable Marker-Less Logarithmic Camera Pose Estimation Engine for Mobile Augmented Reality Processor
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A 27 mW Reconfigurable Marker-Less Logarithmic Camera Pose Estimation Engine for Mobile Augmented Reality Processor

机译:用于移动增强现实处理器的27 mW可重配置的无标记对数照相机姿态估计引擎

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摘要

A marker-less camera pose estimation engine (CPEE) with reconfigurable logarithmic SIMD processor is proposed for the view angle estimation used in mobile augmented reality (AR) applications. Compared to previous marker-based approach, marker-less camera pose estimation can overlay virtual images directly on natural world without the help of markers. However, they require 150x larger computing costs and large power consuming floating-point operations where such requirement severely restricts real-time operations and low-power implementations in mobile platform, respectively. To overcome the gap in computational costs between marker-based and marker-less method, speculative execution (SE) and reconfigurable data-arrangement layer (RDL) are proposed to reduce computing time by 17% and 27%, respectively. For low-power implementation of floating-point units, logarithmic processing element (LPE) is designed to reduce overall power consumption by 18%. The proposed marker-less CPEE is fabricated in 65 nm Logic CMOS technology, and successfully realizes real-time marker-less camera pose estimation with only 27 mW power consumption.
机译:提出了一种带有可重配置对数SIMD处理器的无标记相机姿态估计引擎(CPEE),用于移动增强现实(AR)应用中的视角估计。与以前的基于标记的方法相比,无标记相机姿态估计无需标记即可在自然世界上直接叠加虚拟图像。但是,它们需要150倍的较大计算成本和大量耗电的浮点运算,而这样的要求分别严重限制了移动平台中的实时运算和低功耗实现。为了克服基于标记的方法与基于无标记的方法之间的计算成本差距,提出了推测执行(SE)和可重配置数据安排层(RDL),分别将计算时间减少了17%和27%。对于浮点单元的低功耗实现,对数处理元件(LPE)设计为将总功耗降低18%。提出的无标记CPEE采用65 nm Logic CMOS技术制造,并成功实现了仅27 mW功耗的实时无标记相机姿态估计。

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