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首页> 外文期刊>Solid-State Circuits, IEEE Journal of >A Noise-Cancelling Receiver Front-End With Frequency Selective Input Matching
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A Noise-Cancelling Receiver Front-End With Frequency Selective Input Matching

机译:具有频率选择输入匹配的消除噪声的接收机前端

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This paper presents an inductor-less frequency selective input match wireless receiver front-end utilizing noise cancellation, operational from 0.7 to 3.8 GHz. The main path of the receiver consists of a high input impedance transconductance stage where the output is down-converted to baseband by current mode passive mixers, and then amplified to voltage by a transimpedance amplifier. The output voltage is converted into a current and frequency up-converted by a second set of transconductance stage and mixer. This current is then fed back to the input of the main path, reducing the input impedance, providing input match by means of negative feedback. An auxiliary path with digitally controllable gain is also introduced to cancel the noise of the main path while maintaining high linearity. The chip prototype is fabricated in a 65 nm CMOS process and occupies an active area of 0.15 mm. It achieves a noise figure between 1.6 dB and 3.2 dB depending on the frequency of operation, and an out-of-band IIP2 and IIP3 better than +75 dBm and +1 dBm, respectively. The chip is supplied by 1.2 V and consumes 22.8–34.9 mA.
机译:本文提出了一种利用噪声消除的无电感器频率选择性输入匹配无线接收机前端,工作频率范围为0.7至3.8 GHz。接收器的主要路径包括一个高输入阻抗跨导级,该输出级通过电流模式无源混频器将输出下变频为基带,然后通过跨阻放大器放大为电压。第二组跨导级和混频器将输出电压转换为电流和频率上变频。然后,该电流被反馈到主路径的输入,从而减小了输入阻抗,并通过负反馈提供了输入匹配。还引入了具有数字可控增益的辅助路径,以消除主路径的噪声,同时保持高线性度。该芯片原型是采用65 nm CMOS工艺制造的,其有效面积为0.15 mm。根据工作频率,它的噪声系数在1.6 dB和3.2 dB之间,带外IIP2和IIP3分别优于+75 dBm和+1 dBm。该芯片由1.2 V供电,消耗22.8–34.9 mA。

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