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A 7.2 mW 75.3 dB SNDR 10 MHz BW CT Delta-Sigma Modulator Using Gm-C-Based Noise-Shaped Quantizer and Digital Integrator

机译:使用基于Gm-C的噪声成形量化器和数字积分器的7.2mW 75.3dB SNDR 10MHz BW CTΔ-Σ调制器

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摘要

This paper presents a continuous-time (CT) delta-sigma modulator using a Gm-C based noise-shaped integrating quantizer (NSIQ) with a digital back-end integrator. By incorporating the digital back-end integrator, the tradeoff between resolution and speed for a conventional time-based NSIQ is alleviated. Using only three clock edges and a low-power Gm-C, effective 4-bit quantization with an additional first order noise-shaping is achieved. Also, the linearity requirement of the quantizer is relaxed by employing the digital back-end integrator. The proposed modulator was fabricated in a 0.13 CMOS process with an active area of 0.08 . It operates at 640 MHz and achieves a peak SNDR of 75.3 dB and a peak SFDR of 94.1 dB in a 10 MHz bandwidth while consuming 7.2 mW from a 1.2 V power supply.
机译:本文提出了一种连续时间(CT)Δ-Σ调制器,该调制器使用基于Gm-C的噪声形积分量化器(NSIQ)和数字后端积分器。通过合并数字后端积分器,可以缓解传统基于时间的NSIQ的分辨率和速度之间的折衷。仅使用三个时钟沿和一个低功耗Gm-C,就可以实现有效的4位量化以及额外的一阶噪声整形。而且,通过采用数字后端积分器可以放松量化器的线性要求。所提出的调制器是在0.13 CMOS工艺中制造的,其有效面积为0.08。它的工作频率为640 MHz,在10 MHz带宽中的SNDR峰值为75.3 dB,SFDR峰值为94.1 dB,而1.2 V电源消耗的功率为7.2 mW。

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