A 2 mW, 50 dB DR, 10 MHz BW 5 src='/images/tex/326.gif' alt='times'> Interleaved Bandpass Delta-Sigma Modulator at 50 MHz IF

摘要

A 2 mW 50 dB-DR 10 MHz-BW bandpass (BP) delta-sigma modulator for a digital-IF receiver is presented. It is based on a power-efficient time-interleaved (TI) architecture, which uses a recursive loop and a feed-forward topology. To further improve its power-efficiency, the ADC employs inverter-based OTAs with the help of auxiliary inverters for extra gain. A 0.55 chip is fabricated in a 0.18 CMOS process. Measurements show that the prototype five-path TI BP modulator achieves 50 dB DR and 46 dB SNDR with 10 MHz bandwidth at 50 MHz IF while dissipating only 2 mW.