首页> 外文期刊>Solid-State Circuits, IEEE Journal of >A 0.4 mu text{g} Bias Instability and 1.2 mu text{g}/surd Hz Noise Floor MEMS Silicon Oscillating Accelerometer With CMOS Readout Circuit
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A 0.4 mu text{g} Bias Instability and 1.2 mu text{g}/surd Hz Noise Floor MEMS Silicon Oscillating Accelerometer With CMOS Readout Circuit

机译:具有CMOS读出电路的0.4μ文本{g}偏置不稳定性和1.2μ文本{g} / surd Hz噪声本底MEMS硅振荡加速度计

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摘要

This paper describes a silicon-on-insulator MEMS oscillating accelerometer with a fully differential CMOS continuous-time oscillation sustaining circuit and a digital frequency measurement circuit. To reduce the amplitude-stiffness-induced frequency variation, the effects of flicker noise in the automatic amplitude control circuit are classified into additive and multiplicative components, which are suppressed by chopper stabilization and tail current source free structures, respectively. A low-power digital frequency measurement circuit employing a time-domain Sigma Delta ADC is integrated on chip. The accelerometer achieves a bias instability of 0.4/2 mu text{g} , a bias stability of 4.13/13.2 mu text{g} , and a noise floor of 1.2/2.6 mu text{g} / surd Hz, as measured from the analog/digital outputs, respectively, with a scale factor of 280 Hz/g and a full scale of ±20 g. The chip is fabricated in 0.35 mu text{m} standard CMOS technology, and consumes 4.37 mW under a 1.5 V supply.
机译:本文介绍了一种具有全差分CMOS连续时间振荡维持电路和数字频率测量电路的绝缘体上硅MEMS振荡加速度计。为了减少由振幅刚度引起的频率变化,将自动振幅控制电路中的闪烁噪声的影响分为加法分量和乘法分量,分别通过斩波稳定和无尾电流源结构来抑制。采用时域Sigma Delta ADC的低功耗数字频率测量电路集成在芯片上。从加速度计测得,加速度计的偏置不稳定性为0.4 / 2 mu text {g},偏置稳定性为4.13 / 13.2 mu text {g},本底噪声为1.2 / 2.6 mu text {g} / surd Hz。模拟/数字输出,比例因子分别为280 Hz / g和满量程±20 g。该芯片采用0.35 mu text {m}标准CMOS技术制造,在1.5 V电源下的功耗为4.37 mW。

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  • 来源
    《Solid-State Circuits, IEEE Journal of》 |2017年第2期|472-482|共11页
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  • 作者单位
  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);
  • 原文格式 PDF
  • 正文语种 eng
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