A fully differential sample-and-hold circuit for high-speed applications

摘要

A new design technique for realizing a true fully differential sample-and-hold (S/H) circuit is presented. This technique avoids the reset phase and consequently the need for a high slew rate for the operational amplifier, it therefore can be used for high-speed applications. A prototype circuit, which occupies 0.1 mm/sup 2/ in a 3- mu m CMOS process, is integrated and experimental results are presented.