A 0.4-V$G_{m}$–$C$Proportional-Integrator-Based Continuous-Time$Delta

摘要

This paper presents a G_m-C-based ΔΣ modulator under 0.4-V supply. A 3rd-order continuous-time ΔΣ modulator is proposed by cascading three G_m-C proportional integrators (PIs) with a feedforward resistor for the proportional path, which minimizes the output swing of each integrator and ensures that the last two transconductors operate within their linear input range. A nine-tap finite-impulse response (FIR) digital to analog converter (DAC) in front of the first G_m-C integrator filters the large out-of-band quantization noise from the feedback signal, generating a quiet input of the first transconductor for better linearity. A feedback bias control technique is proposed to achieve a stable transconductance of the G_mcells under low supply voltages. The proposed ΔΣ modulator is fabricated in a 90-nm CMOS and achieves 74.4-dB peak signal-to-noise and distortion ratio (SNDR), 85.2-dB peak spurious free dynamic range (SFDR), and 78.5-dB dynamic range (DR) within a 50kHz bandwidth, which is the first demonstration of G_m-C-based modulators under near-threshold supply voltages. The FoM_wis 61.2 fJ/conversion-step, and FoM_sis 167 dB, outperforming the reported low-voltage ΔΣ modulator designs.