A Sub-mW All-Digital Signal Component Separator With Branch Mismatch Compensation for OFDM LINC Transmitters

摘要

Linear amplification with nonlinear components (LINC) is an attractive technique for achieving linear amplification with high efficiency. This paper presents a sub-mW all-digital signal component separator (SCS) design for OFDM LINC transmitters, including a phase calculator and a digital-control phase shifter (DCPS) pair. In addition, a digital mismatch compensation scheme is proposed and integrated into the SCS to reduce the design complexity of the power amplifier. This chip is manufactured in a 90 nm standard CMOS process with an active area of 0.06$ {hbox{mm}}^{2}$. The DCPS can generate phase-modulated signals at 100 MHz with 8-bit resolution and RMS error 9.33 ps (0.34 $^{circ}$). The phase calculation can be performed at a maximum speed of 50 MHz using a 0.5 V supply voltage, resulting in a 73.88% power reduction. Comparing to state-of-the-art, the power consumption of the overall SCS is only 949.5 $muhbox{W}$ which minimizes the power overhead for an LINC transmitter. This SCS with the branch mismatch compensation provides a 0.02 dB gain and 0.15 $^{circ}$ phase fine-tune resolution without adding additional front-end circuits. Considering 1 dB gain and 10$^{circ}$ phase mismatch, the system EVM of $-$ 29.81 dB and ACPR of $-$ 34.56 dB can still be achieved for 5 MHz bandwidth 64-QAM OFDM signals.