Calibrating for Trapped Charge in Large-Scale ISFET Arrays

摘要

In this paper, we discuss the effect of mismatch due to trapped charge on floating-gate ISFET sensors which constitutes one of its major limitations when fabricated in unmodified CMOS. Especially evident when designing ISFET arrays, mismatch due to trapped charge is significant and random and causes pixels to operate outside their target operating region. Here, we show a gradient descent algorithm that uses a Programmable-Gate in-pixel capacitor to reduce the mismatch across pixels in an iterative and unsupervised manner. Furthermore, we show that this algorithm can be reduced to a single iteration step by estimating in advance the total step of the GD since it depends on a capacitive ratio. We show measured results of both approaches on a 64 x 200 ISFET array which uses a parasitic capacitance across two metal layers in-pixel to obtain a very small PG capacitor. Both approaches are demonstrated across 4 chips and significantly reduce the mismatch spread with comparable performance.