Designer hydride routes to 'Si-Ge'/(Gd,Er)_2O_3/Si(111) semiconductor-on-insulator heterostructures

摘要

We demonstrate Si-Ge integration on engineered M__2O_3/Si(111) (M = Gd.Er) dielectric buffer layers using non-traditional chemical precursors that provide new levels of functionality within the deposition process. Stoichiometric Si_(0.50)Ge_(0.50) alloys and pure Si heterostructures are grown epitaxially via ultra-low-temperature chemical vapor deposition using SiH_3GeH_3 and Si3H_8/Si_4Hio, respectively. In the case of Si on Gd_2O_3, an optimal growth processing window in the range of 500-600 ℃ was found to yield planar layers with monocrystalline structures via a proposed coincidence lattice matching mechanism (2a_(Si)-α_(Gd_2O_3))> while for the SiGe system (2% lattice mismatch) comparable quality films with fully relaxed strain states are deposited at a lower temperature range of 420-450 ℃. Extension of this growth process to Si on Er_2O_3 yields remarkably high-quality layers in spite of the even larger ～3% lattice mismatch. In all cases, the Si-Ge overlayers are found to primarily adopt an A-B-A epitaxial alignment with respect to the M_2O_3 buffered Si(1 1 1). A comparative study of the Si growth using Si_3H_8 and Si_4H_(10) indicates that both compounds provide an efficient and straightforward process for semiconductor growth on Gd_2O_3/Si(1 1 1), which appears to be more viable than conventional approaches from the point of view of scalability and volume.