Statistical study of the influence of LER and MGG in SOI MOSFET

摘要

A 3D drift-diffusion device simulation tool with quantum corrections has been applied to study the off-current, threshold voltage and sub-threshold slope variability induced by the metal gate granularity using a Voronoi approach, and line edge roughness using Fourier synthesis, in a 25 nm Si FinFET. The discretization based on the finite element method allows for an accurate description of the 3D geometry. We have simulated 4000 variations of the device to study the metal gate granularity using four different metal grain sizes. The results for the threshold voltage variability ranged from 8.6 mV, for a 3 nm grain size, to 25.9 mV, for a 10 nm grain size. The effect of the grain size was studied and we found an inverse square root dependence of the variability for the three figures of merit. The mean threshold voltage and sub-threshold slope have monotonous decrease with the decrease in metal grain size suggesting that the device power consumption and switching speed can be improved by reducing the grain size. The corresponding threshold voltage variability can reach up to 8.2 mV when RMS = 3 nm and the correlation length is 50 nm.