Implementation of a new medium voltage asymmetric pulse-width modulation converter with balanced input capacitor voltages

摘要

A 1.44 kW DC/DC converter with zero voltage switching (ZVS) for medium voltage applications is proposed in this study. Two half-bridge circuits with split capacitors are connected in series at high voltage side to limit voltage stresses of power switches at /2. Three DC/DC circuits are adopted to share load current and reduce the current stress of rectifier diodes, transformers and output filter inductors. Two balance capacitors are used in the proposed circuit to automatically balance input split capacitor voltages in every switching cycle. The current doubler rectifier is adopted at low voltage side to partially cancel ripple current so that the root-mean-square current at output capacitor is reduced. Asymmetric pulse-width modulation is used to adjust the duty cycle of power switches and regulate output voltage. The output capacitance of power switches and the external resonant inductance are resonant at the transition interval and power metal-oxide-semiconductor field-effect transistors can be turned on under ZVS. The proposed converter can be applied for high input voltage applications such as a three-phase 380 V/480 V utility system. Experimental results from a 750-800 V input and 24 V/60 A output are provided to demonstrate the performance of proposed converter.