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机译:将NVIDIA GPU线程块调度程序的展示位置策略搅拌,用于并发内核
Department of Computer Science Worcester Polytechnic Institute Worcester MA USA;
Department of Computer Science Worcester Polytechnic Institute Worcester MA USA;
Department of Computer Science Worcester Polytechnic Institute Worcester MA USA;
Department of Computer Science Worcester Polytechnic Institute Worcester MA USA;
Concurrent kernels; GPGPUs; scheduling algorithms;
机译:公平和缓存阻止了GPU上的并发内核执行的意识扭曲调度
机译:cCUDA:GPU上并发内核的有效协同调度
机译:揭开GPU上模版的16×16线程块的神秘面纱
机译:具有并发GPGPU内核的在线结构运行时预测的抢占式线程块调度
机译:GPU上阻塞和非阻塞并发队列的性能评估
机译:具有在线结构运行时预测的抢占式线程块调度,用于并发GpGpU内核