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DATA Processing Using SCAM(4)

机译:使用SCAM的数据处理(4)

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摘要

The SCAM is composed of three main blocks: the controller (SCAMC), the data repository (SCAMD), and the response block (SCAMR), as described in the first article of this series. In order to realize my design, I used ispLEVER Schematic Editor to prepare the logic circuit schematics for the building blocks of the SCAM. The process started with designing the basic cell types representing the bottom of the hierarchy. Figure 1 illustrates those hierarchy cells denoted by "cam_cell," "delimiter_cell," "tag_cell," and "control_cell." A symbol (representing a virtual logic device) was created for each cell type using the ispLEVER Project Navigator process, "Generate Symbolic Symbol" (see the right pane in Figure 1).
机译:SCAM由三个主要模块组成:控制器(SCAMC),数据存储库(SCAMD)和响应模块(SCAMR),如本系列第一篇文章所述。为了实现我的设计,我使用了ispLEVER Schematic Editor来准备SCAM构建块的逻辑电路原理图。该过程从设计代表层次结构底部的基本单元格类型开始。图1说明了由“ cam_cell”,“ delimiter_cell”,“ tag_cell”和“ control_cell”表示的那些层次单元。使用ispLEVER Project Navigator进程为每个单元格类型创建了一个符号(代表虚拟逻辑设备),“ Generate Symbolic Symbol”(参见图1的右窗格)。

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