Design and analysis of wideband low-power LNA for improved RF performance with compact chip area

摘要

Here, a wideband low-noise amplifier (LNA) based on the two-stage cascade configuration is presented to improve the radiofrequency (RF) performance. With the common gate (CG) input stage, the proposed LNA provides wideband input matching, while the wideband gain response was achieved using the peaking inductors inserted at the drain terminals of each stage. With a standardn$0.18, {rm mu m}$0.18μmnCMOS process, the chip area of the proposed wideband LNA is only 0.116 mmn^{2n. However, it consumes a 5.4 mW power from a supply voltage ofn$V_{{rm dd}} = 1, {rm V}$Vdd=1Vn. From the post-layout simulation results, it achieves maximum power gainn$S_{21}$S21nof 11.13 dB at 8.5 GHz, input return lossn$S_{11}$S11nbelow −9.44 dB, reverse isolationn$S_{12}$S12nless than −60 dB, and small group delay variation of ±97 ps across 8.5–20 GHz frequency range. Moreover, noise figure (NF) lies in the range of 2.19–3.23 dB, whereas the NF minimum (n${rm N}{rm F}_{min }$NFminn) varies in the range of 1.55–2.91 dB for 8.5–20 GHz frequency range. Apart from this, the proposed LNA achieves an IIP3 of 0.96 dBm, when a two-tone test is performed with a frequency spacing of 50 MHz.}