$F_{min}$ Design and Performance Analysis of a 866-MHz Low-Power Optimized CMOS LNA for UHF RFID
首页> 外文期刊>Industrial Electronics, IEEE Transactions on >Design and Performance Analysis of a 866-MHz Low-Power Optimized CMOS LNA for UHF RFID
【24h】

Design and Performance Analysis of a 866-MHz Low-Power Optimized CMOS LNA for UHF RFID

机译:用于UHF RFID的866-MHz低功耗优化CMOS LNA的设计和性能分析

获取原文
获取原文并翻译 | 示例
       

摘要

An optimized 866 MHz CMOS LNA for UHF radio-frequency identification reader is presented. It achieves simultaneous impedance and minimum $F_{min}$ noise matching at a very low-power drain of 850 $muhbox{W}$ from a 0.7-V supply voltage. Compared to other GHz LNA designs, this UHF LNA design using sub-1 V supply voltage is quite challenging due to the inductor size and bias drain-related noise factor degradation. The LNA was fabricated using the 130-nm IBM CMOS process. Compared to previously reported narrow-band LNA designs, inclusion of the finite $g_{rm ds}$ effect is found to improve the nanometric design optimization. The low-cost packaged LNA was tested using external lumped element and microstrip line matching. The LNA delivered a power gain $(S_{21})$ of $approx$17 dB and an input power reflection (S11 @ 866 MHz) of $approx-30 hbox{dB}$. It had a minimum pass-band noise figure of around 2.2 dB and a third-order input-referred intercept point of $ approx-11.5 hbox{dBm}$.
机译:提出了一种用于UHF射频识别阅读器的优化866 MHz CMOS LNA。它在850 <公式公式的极低功耗下实现了同时阻抗和最小 $ F_ {min} $ 噪声匹配=“ inline”> $ muhbox {W} $ 由0.7V电源电压供电。与其他GHz LNA设计相比,由于电感器尺寸和与偏置漏极相关的噪声因数降低,使用低于1 V电源电压的UHF LNA设计具有很大的挑战性。 LNA是使用130纳米IBM CMOS工艺制造的。与以前报道的窄带LNA设计相比,发现包含有限的 $ g_ {rm ds} $ 效果可以改善纳米设计优化。使用外部集总元件和微带线匹配测试了低成本封装的LNA。 LNA提供了 $(S_ {21})$ =“ TeX”> $ approx $ 17 dB,输入功率反射(S11 @ 866 MHz)为 $ approx-30 hbox {dB} $ 。它的最小通带噪声系数约为2.2 dB,并且三阶输入参考截点为 $大约11.5 hbox {dBm} $ < / tex>

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号