机译:3D芯片多处理器的内存架构概述
Nanjing Univ, Inst VLSI Design, Key Lab Adv Photon & Elect Mat, Nanjing 210008, Jiangsu, Peoples R China|KTH Royal Inst Technol, Dept Elect Comp & Software Syst, Sch Informat & Commun Technol, Stockholm, Sweden;
Nanjing Univ, Inst VLSI Design, Key Lab Adv Photon & Elect Mat, Nanjing 210008, Jiangsu, Peoples R China;
KTH Royal Inst Technol, Dept Elect Comp & Software Syst, Sch Informat & Commun Technol, Stockholm, Sweden;
KTH Royal Inst Technol, Dept Elect Comp & Software Syst, Sch Informat & Commun Technol, Stockholm, Sweden;
Nanjing Univ, Inst VLSI Design, Key Lab Adv Photon & Elect Mat, Nanjing 210008, Jiangsu, Peoples R China;
Nanjing Univ, Inst VLSI Design, Key Lab Adv Photon & Elect Mat, Nanjing 210008, Jiangsu, Peoples R China;
Nanjing Univ, Inst VLSI Design, Key Lab Adv Photon & Elect Mat, Nanjing 210008, Jiangsu, Peoples R China;
3D integrated circuit; Chip multi-processor; Memory architecture; Non-uniform cache architecture;
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机译:3D多处理器芯片的热建模和分析
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机译:3D多处理器芯片的热建立与分析