A low-power capacitor switching scheme with low common-mode voltage variation for successive approximation ADC

摘要

In this paper, a new low-energy switching technique with low common-mode voltage variation is proposed for successive-approximation analog-to-digital converters (SA-ADCs). In the proposed scheme, not only the switching energy consumed within the first three comparisons is less than zero, but also other comparisons are made with the low-power monotonic method. Therefore, the switching energy of the capacitive array, including the consumed energy during the sampling phase, is reduced by 90.68% compared with the conventional counterpart. Moreover, since the variation of the input common-mode voltage of the employed comparator is only 0.125V(ref), where V-ref f is the reference voltage of the ADC, the required comparator's performance can be Much more relaxed leading to more power saving. Post-layout sinuilation results of a 10-bit 1-MS/s SA-ADC in a 0.18-mu m CMOS technology show a signal-to-noise-and-distortion ratio (SNDR) of 61 dB, a spurious-free dynamic range (SFDR) of 79.8 dB, and an effective number of 9.84 bits. The ADC consumes 35.3 mu W with a 1.8-V supply and achieves a Figure-of-Merit (FoM) of 38.5 fJ/conversion-step.