Dynamic differential signaling based logic families for robust ultra-low power near-threshold computing

摘要

In this paper, novel circuit topologies for near-threshold computing (NTC) are proposed and evaluated. Three separate dynamic differential signaling based logic (DDSL) families are developed in a 130 nm technology to operate at 400 mV and 450 mV. The proposed logic families outperform contemporary CMOS and current-mode logic (CML) circuits implemented for near-threshold. The DDSL families are described as dynamic current-mode logic (DCML), latched DCML (LDCML), and dynamic feedback current-mode logic (DFCML). Simulation and analysis are performed through implementation of boolean functions and a 4x4 bit array multiplier. At a 450 mV supply voltage, the total power of the 4x4 DFCML multiplier is reduced to 0.95x and 0.009x, while the maximum operating frequency is improved by 1.4x and 1.12x as compared to, respectively, a CMOS and CML multiplier. The DCML multiplier consumes 1.48x the power while improving f(max) by 1.65x as compared to a CMOS multiplier. A chain of four inverters implemented with the developed dynamic logic families exhibited an energy delay product (EDP) of 0.27x and 0.016x that of, respectively, CMOS and CML implementations. The mean noise margins, also evaluated with a chain of inverters, of DFCML and LDCML are at least 2.5x greater than that of CMOS.